Texas Instruments taps Swiss nanotech as future of computer chips

Texas Instruments researchers are working with the EPFL. Texas Instruments

In a press release issued in December, Texas Instruments announced that the combination of nanotech and traditional semiconductor processes could be the “future” for computing architecture.

It made the statement based on research it undertook with the Swiss Federal Institute of Technology in Lausanne.

Texas Instruments (TI) presented the evidence behind the statement in a paper at the IEDM in Washington, a confab of the chip industry’s engineering crowd.

It is possible to use single electron transistors (SET) in combination with CMOS to dramatically reduce the size and power consumption of semiconductor devices, said TI in the release.

The idea for a hybrid chip comes from Swiss researchers working at the EPFL’s Micro and Nanoelectronic Devices Group, an interdisciplinary team headed by Adrian Ionescu.

This group believes that SETs and conventional transistors can be combined in a hybrid architecture to carry out logic functions, making them suitable for processing.

TI provided the simulation software to test the Swiss team’s innovation.

An innovative approach

SET devices are radically different to today’s Field Effect Transistors (FETs) devices because they rely on one electron to define the on/off logic state, instead of millions of electrons as is the case with FETs.

It is an important breakthrough because it enables the continuing use of the industry standard CMOS process. Behind it all is the relentless drive to fulfill Moore’s Law, an economic and technology trend that has been driving the price of chips down and the power of processing up for the past three decades.

It is generally believed that the CMOS process will hit a wall in ten to twelve years. Towards solving that problem a range of alternative types of devices have been proposed but most involve using unusual materials and architectures in order to be able to cost effectively manage the signal integrity and heat problems generated when packing transistors so tightly together, according to TI.

Christoph Wasshuber, a TI scientist, who developed the modeling software used to test the Swiss team’s SET hybrid chip, said that it is starting to look “viable for CMOS to continue to play a major role by providing a traditional system interface to millions of radically smaller, lower power, single electron transistors”.

The next challenge for researchers is to manufacture reliably high volumes of SETs in a CMOS compatible process on silicon. To go to the next level the Swiss team has secured funding from the Swiss National Science Foundation to build a prototype over the next two years.

Swiss nanotech

The fact that “nano” is in the title of the Swiss research team is a reflection of the trend towards nano-sized features in the chip manufacturing. As Thomas Egolff ot TAT Ventures, a venture capital fund specialized in chips and medical device technologies, says: “The semiconductor industry is nanotechnology,” suggesting it is not the territory of science fiction.

Ionescu agrees, telling Swiss Venture that companies such as Texas Instruments and NEC are investing in the nanotechnology only because they believe it can be a commercial reality within 5 to 10 years.

By Valerie Thompson